1. Technical Field
Aspects of the present disclosure relate in general to electronic circuitry. In particular, aspects of the disclosure include a test process for Dynamic Random Access Memory (DRAM) in 2.5D/3D System Chips.
2. Description of the Related Art
With conventional two-dimensional (2D) computer chips, a processor and random access memory (RAM) are located on the same plane, and connected via a package substrate.
However, as the electronics industry evolves, chips are now taking advantage of the third dimension—wide input/output dynamic random access memory coupled on top of a processor (3D) or next to a processor via an interposer (2.5D). In such instances, the placement in the third dimension reduces interconnect capacitance between the two components.